1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device.
2. Description of the Related Art
In a large-scale semiconductor memory, a redundancy circuit for failure relieving is provided. It is similarly provided in an electrically erasable programmable flash EEPROM capable of storing data in a non-volatile state. When a defect cell is found through a wafer test, the defect address associated therewith is stored in a redundant memory cell. The redundant memory cell is composed of anon-volatile memory to prevent stored data from being lost even after power-off. In the flash EEPROM the redundant memory cell comprises a memory cell array similar to the normal memory cell array to reduce the cost.
Once the defect address is stored in the redundant memory cell, the defect address data is taken in a data latch circuit for defect address, on initial setting executed after power-on and before the supply voltage reaches a desired voltage that enables normal read/write operation. Then, the data in the data latch circuit is compared with address data fed into an I/O buffer. If a match is detected, a redundancy replacement control is executed in which a decoder circuit is controlled to select a redundant cell instead of the defect cell (see JP 10-302476A, FIGS. 11 and 12, paragraphs 0119-0172, for example).
As described above, in the flash EEPROM the redundant memory cell may be configured as a memory cell array similar to the normal memory cell array. In this case, reading from the redundant memory cell requires the application of a voltage similar to that when a normal memory cell is subject to reading. Specifically, a middle voltage having an almost middle value between a threshold voltage of a memory cell storing “1” data and a threshold voltage of a memory cell storing “0” data must be applied to a word line to read out the defect address data. A variation in production of voltage generators for generating such the middle voltage may occasionally prevent such the middle voltage from being generated accurately. In such the case, the defect address data is read erroneously and the redundancy replacement control can not be executed accurately as a problem.